32 bit alu

[delimanyakcapkin]

elinde logisim programi ile dizayn edilmis 32 bit alu su olan var mi? varsa kral olur...

[aquila]

basligi gorunce bi an titredim, tuylerim diken diken oldu, kolay gelsin kardes.


baskasindan alip odev olarak vermeyi tasvip etmiyoruz ayrica. takildigin yerleri sor, cevap verilsin daha guzel.

[delimanyakcapkin]

abi proje baya buyukde elimde ornek istiyorum aynisini vermek zaten okudugum okul gibi bir yerde intihar manasina gelir.

[rainfall]

2 sınıfta yaptıgım bısey vardı
ısıne yararmı bılmıyorum
module halfadder(a,b,s,c);
input a,b;
output s,c;
xor g1(s,a,b);
and g2(c,b,a);
endmodule

module fulladder(a1,b1,cin,s,cout);
input a1,b1,cin;
output s,cout;
wire s1,c1,c2;
halfadder ha1(a1,b1,s1,c1);
halfadder ha2(cin,s1,s,c2);
or g3(cout,c2,c1);
endmodule

module fourbitadder(a0,a1,a2,a3,cin,b0,b1,b2,b3,s0,s1,s2,s3,cout);
input a0,a1,a2,a3,cin,b0,b1,b2,b3;
output s0,s1,s2,s3,cout;
wire c1,c2,c3;
fulladder fa1(a0,b0,cin,s0,c1);
fulladder fa2(a1,b1,c1,s1,c2);
fulladder fa3(a2,b2,c2,s2,c3);
fulladder fa4(a3,b3,c3,s3,cout);
endmodule

module box3(a0,a1,a2,a3,cin,b0,b1,b2,b3,f0,f1,f2,f3,f4);
input a0,a1,a2,a3,cin,b0,b1,b2,b3;
output f0,f1,f2,f3,f4;
fourbitadder boxx3(a0,a1,a2,a3,1,b0,b1,b2,b3,f0,f1,f2,f3,f4);
endmodule

module box5(a0,a1,a2,a3,cin,b0,b1,b2,b3,f0,f1,f2,f3,f4);
input a0,a1,a2,a3,cin,b0,b1,b2,b3;
output f0,f1,f2,f3,f4;
wire inb0,invb1,invb2,invb3;
not invofb(inb0,invb1,invb2,invb3,b0,b1,b2,b3);
fourbitadder boxx5(a0,a1,a2,a3,1,inb0,invb1,invb2,invb3,f0,f1,f2,f3,f4);
endmodule

module box9(a0,a1,a2,a3,b0,b1,b2,b3,f0,f1,f2,f3);
input a0,a1,a2,a3,b0,b1,b2,b3;
output f0,f1,f2,f3;
and gate1(f0,a0,b0);
and gate2(f1,b1,b1);
and gate3(f2,a2,b2);
and gate4(f3,a3,b3);
endmodule

module box14(a0,a1,a2,a3,b0,b1,b2,b3,f0);
input a0,a1,a2,a3,b0,b1,b2,b3;
wire f1,f2,f3,f4,fo0,fo1,bout0,bout1,bout2,bout3;
output f0;
not n1(bout0,b0);
not n2(bout1,b1);
not n3(bout2,b2);
not n4(bout3,b3);
and (f1,a0,bout0);
and (f2,a1,bout1);
and (f3,a2,bout2);
and (f4,a3,bout3);
or (fo0,f1,f2);
or (fo1,f3,f4);
or (f0,fo0,fo1);
endmodule

module box22(a0,a1,a2,a3,b0,b1,b2,b3,f0,f1,f2,f3);
input a0,a1,a2,a3,b0,b1,b2,b3;
output f0,f1,f2,f3;
xnor gate1(f0,a0,b0);
xnor gate2(f1,b1,b1);
xnor gate3(f2,a2,b2);
xnor gate4(f3,a3,b3);
endmodule

module box28(a0,a1,a2,a3,b0,b1,b2,b3,f0,f1,f2,f3,f4,f5,f6,f7);
input a0,a1,a2,a3,b0,b1,b2,b3;
output f0,f1,f2,f3,f4,f5,f6,f7;
wire sh0,sh1,sh2,sh3,o1,o2,o3,o4,o5,o6,o7,o8,o9,o10,o11,o12,o13,o14,o15,o16,ff0,ff1,ff2,ff3,ff4,ff5,ff6,ff7,ff8;
assign sh0=0;
assign sh1=b0;
assign sh2=b1;
assign sh3=b2;
and g1(o1,a3,sh3);
and g2(o2,a2,sh3);
and g3(o3,a1,sh3);
and g4(o4,a0,sh3);
and g5(o5,a3,sh2);
and g6(o6,a2,sh2);
and g7(o7,a1,sh2);
and g8(o8,a0,sh2);
and g9(o9,a3,sh1);
and g10(o10,a2,sh1);
and g11(o11,a1,sh1);
and g12(o12,a0,sh1);
and g13(o13,a3,sh0);
and g14(o14,a2,sh0);
and g15(o15,a1,sh0);
and g16(o16,a0,sh0);
assign f7=o1;
fourbitadder fa1(o2,o3,o4,0,0,o5,o6,o7,o8,ff0,ff1,ff2,ff3,cout1);
assign f6=ff0;
fourbitadder fa2(ff1,ff2,ff3,cout1,0,o9,o10,o11,o12,ff4,ff5,ff6,ff7,cout2);
assign f5=ff4;
fourbitadder fa3(ff5,ff6,ff7,cout2,0,o13,o14,o15,o16,f4,f3,f2,f1,f0);
endmodule

module box29(a0,a1,a2,a3,b0,b1,b2,b3,f0,f1,f2,f3,f4,f5,f6,f7);
input a0,a1,a2,a3,b0,b1,b2,b3;
output f0,f1,f2,f3,f4,f5,f6,f7;
wire cout,o1,o2,o3,o4,o5,o6,o7,o8,o9,o10,o11,o12,o13,o14,o15,o16,ff0,ff1,ff2,ff3,ff4,ff5,ff6,ff7,ta0,ta1,ta2,ta3;
fourbitadder boxx29(a0,a1,a2,a3,0,1,1,1,1,ta0,ta1,ta2,ta3,cout);
and g1(o1,ta3,b3);
and g2(o2,ta2,b3);
and g3(o3,ta1,b3);
and g4(o4,ta0,b3);
and g5(o5,ta3,b2);
and g6(o6,ta2,b2);
and g7(o7,ta1,b2);
and g8(o8,ta0,b2);
and g9(o9,ta3,b1);
and g10(o10,ta2,b1);
and g11(o11,ta1,b1);
and g12(o12,ta0,b1);
and g13(o13,ta3,b0);
and g14(o14,ta2,b0);
and g15(o15,ta1,b0);
and g16(o16,ta0,b0);
assign f7=o1;
fourbitadder fa1(o2,o3,o4,0,0,o5,o6,o7,o8,ff0,ff1,ff2,ff3,cout1);
assign f6=ff0;
fourbitadder fa2(ff1,ff2,ff3,cout1,0,o9,o10,o11,o12,ff4,ff5,ff6,ff7,cout2);
assign f5=ff4;
fourbitadder fa3(ff5,ff6,ff7,cout2,0,o13,o14,o15,o16,f4,f3,f2,f1,f0);
endmodule

module alu(a0,a1,a2,a3,b0,b1,b2,b3,f0,f1,f2,f3,f4,f5,f6,f7,s0,s1,s2,f0,f1,f2,f3,f4,f5,f6,f7);
input a0,a1,a2,a3,b0,b1,b2,b3,s0,s1,s2;
output f0,f1,f2,f3,f4,f5,f6,f7;
box3 boxx3(a0,a1,a2,a3,cin,b0,b1,b2,b3,f0,f1,f2,f3,f4);
box5 boxx5(a0,a1,a2,a3,cin,b0,b1,b2,b3,f0,f1,f2,f3,f4);
box9 boxx9(a0,a1,a2,a3,b0,b1,b2,b3,f0,f1,f2,f3);
box14 boxx14(a0,a1,a2,a3,b0,b1,b2,b3,f0);
box22 boxx22(a0,a1,a2,a3,b0,b1,b2,b3,f0,f1,f2,f3);
box28 boxx28(a0,a1,a2,a3,b0,b1,b2,b3,f0,f1,f2,f3,f4,f5,f6,f7);
box29(a0,a1,a2,a3,b0,b1,b2,b3,f0,f1,f2,f3,f4,f5,f6,f7);
//We don't have enough time to write multiplexers for these boxs' results.

endmodule

[delimanyakcapkin]

tesekkur ediyorum cok sagol.